(1) Field of the Invention
The present invention relates to a process in which complimentary metal oxide semiconductor, (CMOS), field effect transistors, are fabricated, with specific process steps included to improve CMOS performance while reducing the risk of yield and reliability failures.
(2) Description of Prior Art
Very large scale integration, (VLSI), has allowed the semiconductor chip industry to increase circuit density while still maintaining, or reducing cost. This has been accomplished by ability of the semiconductor industry to fabricate silicon devices with sub-micron features, or micro-miniaturazation. The attainment of sub-micron features has been achieved mainly by advances in specific semiconductor fabrication disciplines, such as photolithography and reactive ion etching, (RIE). The use of more sophisticated exposure cameras, as well as the development of more sensitive photoresist materials, have allowed sub-micron images in photoresist to be routinely obtained. Similar advances in dry etching tools and processes have resulted in the successful transfer of these sub-micron images in photoresist, to underlying materials, used for the fabrication of advanced CMOS devices.
However with the trend to smaller devices, specific yield and performance detractors, as well as reliability risks, become more prevalent. For example as the ate insulator of a CMOS device becomes thinner, in an attempt to improve device performance, the possibility of yield loss, due to insulator breakdown becomes greater. In addition as the channel length of the CMOS device becomes shorter, again to improve performance, the reliability risk of hot electron injection increase. Narrower channel lengths also present yield problems in terms of junction punchthrough. As the channel length of a CMOS device shortens, the space between depletion regions, created from the source region and the substrate, and from the drain region and substrate, decrease. This close proximity, or touching of depletion regions, can result in punchthrough leakages, or yield detractors. In addition salicide, (Self-Aligned silICIDE), bridging, or the inability to completely separate the silicide formed on the source and drain regions, from the salicide formed on the gate structure of a CMOS device, can also result in yield loss.
Several solutions for these phenomena, occurring with narrow channel length CMOS devices, have been previously described. For example Jang, in U.S. Pat. No. 5,439,839, as well as Nasr, in U.S. Pat. No. 4,912,061, have described processes in which salicide bridging is addressed via use of a disposable sidewall spacer. However this invention will describe a CMOS process that will offer yield enhancements, regarding decreased salicide bridging, via use of a disposable sidewall spacer, formed via use of a dual insulator spacer structure. However in this invention the removal of part of the dual insulator spacer exposes a peripheral channel region, in which a pocket ion implantation procedure, used to reduce source and drain punchthrough leakage, is performed. In addition the incorporation of an ultra shallow ion implantation region, used to decrease the resistance between the silicide on the source and drain region, and the channel region, is also included in the peripheral channel region. These process steps enable sub-quarter micron CMOS devices, with enhanced yield and performance to be realized.